1. Field of the Invention
The present invention relates to a semiconductor memory device including an ODT (On Die Termination) circuit
2. Description of Related Art
An operation speed of a PC, a server, a work station, and the like is increased. Then, amplitude of a signal is gradually reduced between semiconductor memory devices in order to minimize delay time in signal transmission. Accordingly, an impedance matching circuit called an ODT (On Die Termination) is mounted on the semiconductor memory device on a receiving side required to increase the operation speed as a countermeasure against noise and impedance mismatch.
FIG. 1 shows a configuration of a semiconductor memory device disclosed in Japanese Patent Application Publication (JP-P2004-310981A) as a conventional semiconductor memory device. The semiconductor memory device includes an ODT (On Die Termination) circuit 30, a pull-up transistor PM and a pull-down transistor NM in an output buffer, and an input buffer 31.
The pull-up transistor PM and the pull-down transistor NM are connected in series to each other. The pull-up transistor PM is connected to a supply voltage node to which a power supply voltage VDDQ is supplied. The pull-down transistor NM is connected to a ground voltage node to which a ground voltage VSSQ is supplied. An input of the input buffer 31 is connected to an intermediate node between the pull-up transistor PM and the pull-down transistor NM. A data input/output port DQ is connected to the intermediate node.
The ODT circuit 30 is provided between a termination voltage port VTT and the intermediate node. The ODT circuit 30 includes a termination resistance R-term1 and a switch TM. The intermediate node is connected to one end of the termination resistance R-term1. The switch TM is provided between the other end of the termination resistance R-term1 and the termination voltage port VTT. The switch TM is a transfer gate including an n-type MOS transistor and a p-type MOS transistor. The switch TM selectively couples the termination voltage port VTT with the other end of the termination resistance R-term1 in response to a termination enable signal DQ_TE and an inverted signal DQ_TEB thereof.
As described above, in the semiconductor memory device, terminations of the data input/output port DQ and of a transmission line DB connected to the data input/output port DQ are required to suppress reflection of input data. Since the data input/output port DQ is provided for an input/output bidirectional bus, the ODT circuit 30 is disabled in a read mode and the ODT circuit 30 is enabled in other modes Although a clear description is not found in the above-mentioned Japanese Patent Application Publication (JP-P2004-310981A), the enable state and the disabled state are controlled through a logic operation with a read mode, by newly adding an MRS (Mode Resister Set) control circuit or newly adding a memory controller and an ID (Identity) register, for the ODT control of the data input/output port DQ.
However, an address/command system signal also needs to be terminated in the ODT circuit as an operation frequency increases. In case of mounting the ODT circuit of the address/command system on a synchronous semiconductor memory device, a complex dedicated design for timing control is required for the ODT enable/disenable control. That is, an address/command input for control by the ODT circuit to the data input/output port DQ requires a control by another ODT circuit. In addition, a control logical circuit dedicated to that control is required, which increases a circuit size.